Inspection

Key issues

Advancing the state of the art in IC manufacturing will require new substrates, new materials and greater process integration. For example, creating thin films for the 32 nm technology node and beyond will involve large wafer sizes up to 450 mm, the integration of new materials such as silicon-on-insulator (SOI) and quartz, epi layers, numerous rapid thermal processing (RTP) steps, and through-silicon-via (TSV) constructions.

At the 32 nm node, new types of defects such as crystalline defects from dislocations, pin marks, staking faults and surface pits are generated, which greatly impacts yield. Without a cost-effective means of locating and identifying such faults, the performance of subsequent processing steps will suffer. Lithography performance, which relies on the desired image’s interaction with a substrate’s surface, and TSV technology, which will be used in most emerging high-volume consumer applications, will be affected.

Systematic inspection of the front-side, back-side and edge of substrates is becoming more critical – both to provide holistic, 360-degree wafer inspection as well as to increase the productivity and return on investment from today’s multi-billion-dollar fabs. Holistic inspection needs will only increase as the industry continues to drive toward greater cost efficiencies by increasing substrate sizes beyond 300 mm diameters to 450 mm.

The Altatech solution

Available for: Silicium, SOI, EpiSi, Quartz, GaN, GaS, SiC, Sapphire, SoS and other engineered susbtrates.

Altatech combines the following technologies to provide accurate and full substrate information.

Edge inspection

Proprietary sensor design with:

Detection, classification and measurement of macro defects on substrate edge, bevels and apex.
High depth of focus with high resolution detection.
High speed acquisition.

Edge inspection